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Microprocessor architecture : from simple pipelines to chip multiprocessors / Jean-Loup Baer.
Publication details: New York : Cambridge University Press, 2010.Description: xiv, 367 p. : ill. ; 26 cmContent type:- text
- unmediated
- volume
- 9780521769921 :
- 0521769922 :
- QA76.5 .B227 2010
Contents:
Summary: This book describes the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars.
1. Introduction; 2. The basics; 3. Superscalar processors; 4. Front-end: branch prediction, instruction fetching, and register renaming; 5. Back-end: instruction scheduling, memory access instructions, and clusters; 6. The cache hierarchy; 7. Multiprocessors; 8. Multithreading and (chip) multiprocessors; 9. Current limitations and future challenges.
| Item type | Current library | Home library | Shelving location | Call number | Status | Barcode | |
|---|---|---|---|---|---|---|---|
Books
|
American University in Dubai | American University in Dubai | Main Collection | QA 76.5 .B227 2010 (Browse shelf(Opens below)) | Available | 5062166 |
1. Introduction; 2. The basics; 3. Superscalar processors; 4. Front-end: branch prediction, instruction fetching, and register renaming; 5. Back-end: instruction scheduling, memory access instructions, and clusters; 6. The cache hierarchy; 7. Multiprocessors; 8. Multithreading and (chip) multiprocessors; 9. Current limitations and future challenges.
This book describes the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars.
Includes bibliographical references (p. 351-360) and index.
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